1. Field of the Invention
The invention relates to a semiconductor memory apparatus.
2. Description of the Related Art
Semiconductor memory apparatuses in which stored data are read out at double data rate relative to an external, incoming clock signal are now widely used, particularly for high speed applications. In such “DDR-DRAMs”, the phase or timing of the output data DQ is specified by a data read clock signal, which is conventionally called the DQS signal.
In this context, the phase of the data read clock signal DQS has its phase angle adjusted in relation to the input, external clock signal CLK using a phase adjustment device. The phase adjustment device is often a “DLL” (Delay Locked Loop) circuit which feeds a “clock tree” for supplying the semiconductor memory apparatus with an internal clock signal.
The phase angle of the data read clock signal DQS is subject to numerous different interfering effects which means that in some cases it does not match the nominally desired phase angle. For example, although the phase adjustment device, i.e., the DLL circuit, can compensate for slow variations in internal delays in the DLL circuit, brief fluctuations caused by voltage fluctuations, for example, cannot be equalized by the phase adjustment device.
The actual phase angle of the data read clock signal DQS in a DDR-DRAM therefore needs to be tested as part of a test in a semiconductor memory apparatus. In addition, it is conventionally necessary for a test apparatus to detect the data DQ which are output from the semiconductor memory apparatus, taking into account the phase angle of the data read clock signal DQS, which is called “source synchronous sampling”.
However, testing the actual phase angle of the data read clock signal DQS and detecting the output data DQ by means of a test taking into account the phase angle of the data read clock signal DQS require complex high speed test tools which—if they are actually available—result in high costs.